This invention relates generally to printed circuit boards and more specifically to high speed printed circuit boards that minimize undesirable signal reflections in a via.
As is known in the art, conductive traces are formed on a printed circuit board (“PCB”) for carrying data signals and power between components mounted on the board. Space considerations often require the use of multi-layer PCBs including multiple layered dielectric substrates with conductive traces or planes formed on each substrate. The layered substrates are held together to make a PCB that has conductive traces on different levels within the board.
In order to interconnect conductive traces on different layers, conductive vias extend between layers of the multi-layer PCB. For this purpose, conductive vias intersect vertically aligned pads joined to conductive traces on different layers. Conductive vias also interconnect components mounted on the board to conductive traces on inner layers of the board. More particularly, a contact of the component, such as a press-fit pin, makes contact with the conductive walls of the via and the conductive walls of the via, in turn, contact one or more pads of conductive traces on inner layers of the board. Vias which extend through all layers of a multi-layer board are sometimes referred to as through-holes.
Conductive vias are usually formed after the layered substrates are formed into a board. The vias are typically formed by drilling holes through at least a portion of the board and plating the walls of the holes with a conductive material, such as copper. Typically, a thin layer of copper is applied by an electroless process. An electrical potential is connected to this thin layer of copper and a thicker layer of copper is deposited over the thin layer by an electrolytic deposition process. In order to ensure reliable plating of the via walls, the aspect ratio of the printed circuit board thickness to the via diameter is limited. For example, for a PCB having a thickness on the order of 0.25 inches (6.35 mm), the diameter of a plated via must be on the order of at least 0.018 inches (0.46 mm) requiring the hole to be on the order of 0.020 inches (0.51 mm) for plating thickness on the order of 0.002 inches (0.05 mm). This minimum via diameter limits the number of vias that can be provided in a given circuit board area.
An illustrative multi-layer PCB 10 having a conductive via (plated through-hole) 14 as known in the art is shown in FIG. 1. The printed circuit board 10 includes dielectric layers 12a, 12b, and 12c, with a conductive trace 16 formed on layer 12b. In this example, a three layer PCB is shown. The conductive via 14 extends through a pad 17 of signal trace 16 in order to electrically interconnect to the signal trace 16. A pin 26 of a component 28 inserted at least partially into the conductive via 14 contacts the conductive walls of the via and thus, is electrically connected to signal trace 16.
One of the disadvantages associated with utilization of conductive vias relate to signal quality at high data rates. For example, portions of a conductive via extending beyond the inner layers of the board which are interconnected to other layers and/or to a component mounted on the board, such as portion 20 of via 14, can act as a resonant stub, causing undesirable signal reflections at certain frequencies.
A solution to this problem is to use “blind” or buried vias for interconnecting traces on inner layers of a PCB. A blind via extends from the surface of a board through only a portion of the layers of a multi-layer PCB. Buried vias are used to interconnect two interior layers of the printed circuit board. Buried vias are formed by first making a subassembly from one or more layers of the PCB. A hole is drilled through these layers and the hole is plated. Additional substrate layers are added to the top and the bottom of the subassembly to make a complete PCB. The resulting buried vias are inaccessible and increase the manufacturing complexity of the multi-layer PCB.
An alternative technique for eliminating resonant stubs formed by portions of conductive vias is to remove the stub portions of the via by drilling them out of the board. For example, by drilling a hole through layers 12b and 12c concentrically around, and with a larger diameter than the via 14, the via portion 20 extending through layers 12b and 12c is removed. However, this technique requires additional manufacturing steps that add undesirable cost and complexity.
Still another solution provided for eliminating resonant stubs formed by portions of conductive vias is shown in FIG. 2. This drawing is FIG. 3 of U.S. application Ser. No. 09/892,045, now U.S. Pat. No. 6,593,535, issued Jul. 15, 2003, that is entitled “Direct Inner Layer Interconnect For A High Speed Printed Circuit Board” and assigned to the assignee of the present invention. A multi-layer PCB 30 having dielectric layers 34, 36, 38 and 40 is illustrated. At least one of the dielectric layers has a conductive trace 44 formed thereon for carrying a high speed signal. The conductive trace 44 includes a pad 44a to facilitate electrical connection to the trace 44.
Unlike the other prior art solutions described above, FIG. 2 shows a non-conductive via 54 in the form of a non-plated hole extending through at least a portion of the dielectric layers 34–40 to intersect the conductive trace 44. A conductive element 60, such as a contact of an electrical component (e.g., connector or integrated circuit), is designed to be press-fit into the non-conductive via 54 to make electrical contact with the pad 44a of the trace 44. While this solution offers advantages, it does require manufacturing and design steps to ensure that the conductive element 60 makes satisfactory electrical contact with the desired conductive trace of the PCB. Also, where two inner traces of the PCB are desired to be electrically connected to the conductive element 60, additional steps and complexities are added.
What is desired, therefore, is an easily manufactured structure for making reliable electrical connection to a conductive trace on an inner layer of a multi-layer PCB that minimizes undesirable signal reflections due to resonant stubs.